Py4Hw User Guide

Py4Hw is a Python library that allows to describe, display, simulate, and generate Verilog for digital circuits without the need of any other HDL tool.

In this notebook we will learn how to use it. Launch it in Binder by clicking the icon of the README.md for an better user experience.

Follow it step by step for an incremental view of the library or browse the following table of contents.

0. Setting Up (Not necessary if running from Binder)

0.1 Installing the library

0.2 Cloning the development repository

1. Basics

1.1 Hardware Design Style

1.2 Object Oriented Approach

1.3 HWSystem

1.4 Logic

1.5 Ports

1.6 Wires

1.7 Parameters

1.8 Interfaces

1.9 Abstract Logic

2. Combinational Primitive Blocs

2.1 Bitwise Logic Operations

2.2 Logical and Relational Operations

2.3 Bit manipulation

3. Sequential Primitive Blocks

3.1 Registers

3.2 Memories

4. Advanced Sequential Blocks

4.1 FSMs

4.2 Clocked Processes (Algorithmic Design Style)

4.3 Clock enabling

5. Simulation

5.1 The simulator

5.2 Scopes

5.3 Waveforms

6. Visualization

6.1 Schematic Viewer

6.2 Manipulating Schematics

6.3 Interactive Workbench

7. Verilog Synthesis

7.1 RTL Generation from Strucrual Descriptions

7.2 RTL Generation from Behavioural Descriptions

8. Advanced Features

8.1 Dealing with unique instances, unique blocks and parametetric blocks

9. IP library

9.1 Current blocks

9.2 Future goals

10. Internals

10.1 Behavioural Modeling

10.2 Cycle Based Simulation

10.3 Schematic Visualization

10.4 Comparing with other Python based HDLs

11. High Level Synthesis

11.1 HLS of combinational circuits