Py4Hw User Guide> 7.1 RTL Generation from Structural Descriptions¶

Next: 7.2 RTL Generation from Behavioural Descriptions¶

py4hw generates Verilog RTL Code.

As many high level language RTL generation tool, it (still) creates HDL code which is ugly to the eyes of a typical Hardware designer.

The reason for this is explained in section 8.1, but we are working to improve significantly this issue compared with other similar frameworks.

In [1]:
import py4hw

class Circuit(py4hw.Logic):
    
    def __init__(self, parent, name, a, b, r, c):
        super().__init__(parent, name)
        
        a = self.addIn('a', a)
        b = self.addIn('b', b)
        r = self.addOut('r', r)
        c = self.addOut('c', c)

        py4hw.Or2(self, 'or', a,b,r)
        py4hw.Xor2(self, 'xor', a,b,c)
        
        
sys = py4hw.HWSystem()
a = sys.wire('a', 1)
b = sys.wire('b', 1)
c = sys.wire('c', 1)
r = sys.wire('r', 1)

ha = Circuit(sys, 'half_adder', a, b, r, c)

rtlgen = py4hw.VerilogGenerator(ha)

print(rtlgen.getVerilog(noInstanceNumber=True))

// This file was automatically created by py4hw Verilog generator
module Circuit (
	input  a,
	input  b,
	output  r,
	output  c);

assign r = a | b;
assign c = a ^ b;
endmodule

py4hw uses different techniques to generate the Verilog for different type of circuits. In some simple primitive circuits (like and, or, etc) py4hw uses inlining to automatically embed assign expressions in the output Verilog code.

Summary¶

  • Verilog generation from structural descriptions is straight forward
  • In some cases (for simple well-known operations) it uses inlining
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