Lesson 4 - Seven Segments Display

We can create a combinational circuit that converts an hexadecimal digit into a representation in a seven segments display

import sys
import platform
if (platform.uname().node == 'TPY14'):
    print('Dev machine')
    sys.path.append('..\\..\\..\\py4hw')

import math
import numpy as np
import py4hw
import matplotlib.pyplot as plt

The combinational functions of a seven segments display

A seven segments digplay is usually implemented with 7 LEDs organized as follows

   ___
 _|_a_|_
| |   | |
|f|   |b|
|_|___|_|
  |_g_|
| |   | |
|e|   |c|
|_|___|_|
  |_d_|

actually, we can have LED[6..0] = {gfedcba}

We have to do the following table:

value	gfedcba
0000	0111111
0001	0000110
0010	1011011
0011	1001111
0100	1100110
0101	1101101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

a = 0 , 2 , 3 , 5 , 6 , 7 , 8 , 9 , 0xA , 0xC , 0xE , 0xF

b = 0 , 1 , 3, 4, 7, 8, 9, 0xA, 0xd

c = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xA, 0xb, 0xd

d = 0, 2, 3, 5, 6, 8, 0xb, 0xC, 0xd, 0xE

e = 0, 2, 6, 8, 0xA, 0xb, 0xC, 0xd, 0xE, 0xF

f = 0, 4, 5, 6, 8, 9, 0xA, 0xb, 0xC, 0xE, 0xF

g = 2, 3, 4, 5, 6, 8, 9, 0xA, 0xb, 0xd, 0xE, 0xF

class Digit7Segment(py4hw.Logic):
    def __init__(self, parent, name, v, led):
        super().__init__(parent, name)
        
        assert(led.getWidth() == 7)
        
        self.addIn('v', v)
        self.addOut('led', led)
        
        
        a_minterms = [0,2,3,5,6,7,8,9,0xA,0xC,0xE,0xF]
        b_minterms = [0,1,2,3,4,7,8,9,0xA,0xd]
        c_minterms = [0,1,3,4,5,6,7,8,9,0xA,0xb,0xd]
        d_minterms = [0,2,3,5,6,8,0xb,0xC,0xd,0xE]
        e_minterms = [0,2,6,8,0xA,0xb,0xC,0xd,0xE,0xF]
        f_minterms = [0,4,5,6,8,9,0xA,0xb,0xC,0xE,0xF]
        g_minterms = [2,3,4,5,6,8,9,0xA,0xb,0xd,0xE,0xF]
        
        
        a = self.wire('a')
        b = self.wire('b')
        c = self.wire('c')
        d = self.wire('d')
        e = self.wire('e')
        f = self.wire('f')
        g = self.wire('g')
        
        na = self.wire('na')
        nb = self.wire('nb')
        nc = self.wire('nc')
        nd = self.wire('nd')
        ne = self.wire('ne')
        nf = self.wire('nf')
        ng = self.wire('ng')
        
        py4hw.ConcatenateLSBF(self, 'led', [a,b,c,d,e,f,g], led)
        
        py4hw.SumOfMinterms(self, 'a', v, a_minterms, na)
        py4hw.SumOfMinterms(self, 'b', v, b_minterms, nb)
        py4hw.SumOfMinterms(self, 'c', v, c_minterms, nc)
        py4hw.SumOfMinterms(self, 'd', v, d_minterms, nd)
        py4hw.SumOfMinterms(self, 'e', v, e_minterms, ne)
        py4hw.SumOfMinterms(self, 'f', v, f_minterms, nf)
        py4hw.SumOfMinterms(self, 'g', v, g_minterms, ng)
        
        py4hw.Not(self, 'na', na, a)
        py4hw.Not(self, 'nb', nb, b)
        py4hw.Not(self, 'nc', nc, c)
        py4hw.Not(self, 'nd', nd, d)
        py4hw.Not(self, 'ne', ne, e)
        py4hw.Not(self, 'nf', nf, f)
        py4hw.Not(self, 'ng', ng, g)

Custom visual feedback

One of the main benefits of using python is that we can use it to create visual feedback from the collected values to simplify the interpretation of the signals. Hence, verification is much simpler than looking at waveforms.

def drawSevenSegments(i, v):
    plt.subplot(1,16,i+1)

    sp = 0.5
    ll = 5
    hx = np.array([0, sp, ll-sp, ll, ll-sp, sp])
    hy = np.array([0, sp, sp, 0, -sp, -sp])
    vx = np.array([0, sp, sp, 0, -sp, -sp])
    vy = np.array([0, sp, ll-sp, ll, ll-sp, sp])
    led_x=[None]*7
    led_y=[None]*7

    led_x[0] , led_y[0] = hx , hy + 2*ll     # LED a
    led_x[1] , led_y[1] = vx + ll, vy + ll     # LED b
    led_x[2] , led_y[2] = vx + ll, vy      # LED c
    led_x[3] , led_y[3] = hx , hy     # LED d
    led_x[4] , led_y[4] = vx , vy      # LED e
    led_x[5] , led_y[5] = vx , vy + ll     # LED f
    led_x[6] , led_y[6] = hx , hy + ll     # LED g
    
    vi = v.get()
    for i in range(7):
        if (not(vi & 1)):
            plt.fill(led_x[i], led_y[i], edgecolor='black', facecolor='red')
        vi = vi >> 1
    
    plt.xlim(-sp,ll+sp)
    plt.ylim(-sp, 2*ll+sp)
    plt.axis('off')

Testing

We do a simple test iterating all the hexadecimal values

hw = py4hw.HWSystem() 
hlp = py4hw.LogicHelper(hw)

w = hw.wire('w', 4)
led = hw.wire('led', 7)
reset = hlp.hw_constant(1,0)
inc = hlp.hw_reg(hlp.hw_constant(1,1))

py4hw.Counter(hw, 'count', inc=inc, reset=reset, q=w)
Digit7Segment(hw, 'seve', w, led)

plt.figure(figsize=(16,2))

for i in range(16):
    hw.getSimulator().clk()
    drawSevenSegments(i, led)
    

plt.show()

class TestLED(py4hw.Logic):
    def __init__(self, parent, name, values, leds):
        super().__init__(parent, name)
        
        values = values.copy()
        values.reverse()
        
        for idx, led in enumerate(leds):
            self.addOut('led{}'.format(idx), led)
            
            v =  self.wire('v{}'.format(idx), 4)
            #lw =  self.wire('led{}'.format(idx), 7)

            py4hw.Constant(self, 'k{}'.format(idx), values[idx], v)
            Digit7Segment(self, 'sv{}'.format(idx), v, led)

hw = py4hw.HWSystem() 

leds = []
for i in range(6):
    w = hw.wire('led{}'.format(i), 7)
    leds.append(w)
    
#dut = TestLED(hw, 'test', [0xC, 0xA, 0xF, 0xE, 0x2, 0x3], leds)
dut = TestLED(hw, 'test', [3, 0, 0, 3, 2, 3], leds)

sch = py4hw.Schematic(dut.children['sv0'])
sch.draw()

Generating Verilog

The current Verilog generation generates a module for every instance of the hierarchy. This is inneficient because it generates a long descriptions, while many modules are exactly the same. Although this is a current issue, soon, in future releases this will be solved.

The previous example was synthesized and tested in a Terasic DE1 board.

rtl = py4hw.VerilogGenerator(dut)
print(rtl.getVerilogForHierarchy())

// This file was automatically created by py4hw RTL generator
module TestLED (
	output [6:0] led0,
	output [6:0] led1,
	output [6:0] led2,
	output [6:0] led3,
	output [6:0] led4,
	output [6:0] led5);
wire [3:0] w_v0;
wire [3:0] w_v4;
wire [3:0] w_v2;
wire [3:0] w_v1;
wire [3:0] w_v5;
wire [3:0] w_v3;

assign w_v0[3:0] = 3;
Digit7Segment_2b120941988 i_sv0(.v(w_v0),.led(led0));
assign w_v1[3:0] = 2;
Digit7Segment_2b120b5e248 i_sv1(.v(w_v1),.led(led1));
assign w_v2[3:0] = 3;
Digit7Segment_2b120cc7408 i_sv2(.v(w_v2),.led(led2));
assign w_v3[3:0] = 0;
Digit7Segment_2b120e316c8 i_sv3(.v(w_v3),.led(led3));
assign w_v4[3:0] = 0;
Digit7Segment_2b120f969c8 i_sv4(.v(w_v4),.led(led4));
assign w_v5[3:0] = 3;
Digit7Segment_2b121101c88 i_sv5(.v(w_v5),.led(led5));
endmodule

// This file was automatically created by py4hw RTL generator
module Digit7Segment_2b120941988 (
	input [3:0] v,
	output [6:0] led);
wire w_f;
wire w_c;
wire w_nf;
wire w_na;
wire w_ne;
wire w_a;
wire w_d;
wire w_nd;
wire w_g;
wire w_e;
wire w_nb;
wire w_b;
wire w_ng;
wire w_nc;

assign led ={w_g,w_f,w_e,w_d,w_c,w_b,w_a};
SumOfMinterms_2b1209f4648 i_a(.a(v),.r(w_na));
SumOfMinterms_2b120a2e688 i_b(.a(v),.r(w_nb));
SumOfMinterms_2b120a5f3c8 i_c(.a(v),.r(w_nc));
SumOfMinterms_2b120a960c8 i_d(.a(v),.r(w_nd));
SumOfMinterms_2b120ac4588 i_e(.a(v),.r(w_ne));
SumOfMinterms_2b120af35c8 i_f(.a(v),.r(w_nf));
SumOfMinterms_2b120b25288 i_g(.a(v),.r(w_ng));
assign w_a = ~w_na;
assign w_b = ~w_nb;
assign w_c = ~w_nc;
assign w_d = ~w_nd;
assign w_e = ~w_ne;
assign w_f = ~w_nf;
assign w_g = ~w_ng;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b1209f4648 (
	input [3:0] a,
	output  r);
wire w_s11;
wire w_bits_0;
wire w_s0;
wire w_bits_3;
wire w_s1;
wire w_s3;
wire w_s8;
wire w_s9;
wire w_s2;
wire w_s4;
wire w_bits_2;
wire w_s7;
wire w_bits_1;
wire w_s10;
wire w_s6;
wire w_s5;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b1209fb908 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b1208cee08 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120a01188 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120a04388 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120a13f88 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120a2c808 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120a29c48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120a09648 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120a0cd48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120a15348 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120a19a48 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120a20e88 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1209fb908 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1208cee08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a01188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a04388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a13f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a2c808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a29c48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a09648 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a0cd48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a15348 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a19a48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a20e88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120a2e688 (
	input [3:0] a,
	output  r);
wire w_s9;
wire w_bits_0;
wire w_s8;
wire w_bits_3;
wire w_s4;
wire w_s1;
wire w_s2;
wire w_s3;
wire w_bits_1;
wire w_s5;
wire w_s6;
wire w_s7;
wire w_s0;
wire w_bits_2;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120a31088 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120a33d48 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120a39748 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120a3f148 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120a41848 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120a45388 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120a487c8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120a4e1c8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120a528c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120a53e88 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a31088 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a33d48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a39748 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a3f148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a41848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a45388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a487c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a4e1c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a528c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a53e88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120a5f3c8 (
	input [3:0] a,
	output  r);
wire w_s1;
wire w_s2;
wire w_s11;
wire w_bits_1;
wire w_s6;
wire w_s9;
wire w_s0;
wire w_s7;
wire w_s8;
wire w_bits_2;
wire w_s3;
wire w_s4;
wire w_s5;
wire w_bits_0;
wire w_s10;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120a5fd88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120a63a88 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120a6a488 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120a6db88 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120a71588 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120a73dc8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120a79508 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120a7b948 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120a81348 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120a85908 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120a89048 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120a8c488 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a5fd88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a63a88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a6a488 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a6db88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a71588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a73dc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a79508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a7b948 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a81348 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a85908 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a89048 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a8c488 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120a960c8 (
	input [3:0] a,
	output  r);
wire w_bits_2;
wire w_s3;
wire w_s6;
wire w_bits_0;
wire w_bits_3;
wire w_s8;
wire w_s1;
wire w_s2;
wire w_s4;
wire w_bits_1;
wire w_s7;
wire w_s5;
wire w_s9;
wire w_s0;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120a96a88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120a9c788 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120aa1188 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120aa4888 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120aa7f88 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120aac808 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120ab1208 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120ab5648 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120ab7d48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120abc088 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a96a88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120a9c788 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120aa1188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120aa4888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120aa7f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120aac808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ab1208 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ab5648 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ab7d48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120abc088 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120ac4588 (
	input [3:0] a,
	output  r);
wire w_bits_1;
wire w_s1;
wire w_s2;
wire w_bits_2;
wire w_s0;
wire w_s7;
wire w_s3;
wire w_s4;
wire w_s8;
wire w_s9;
wire w_bits_0;
wire w_s5;
wire w_bits_3;
wire w_s6;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120ac4f88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120ac9c88 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120acf688 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120ad2d88 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120ad7788 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120adafc8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120adf448 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120ae1b48 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120ae3f88 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120aea388 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ac4f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ac9c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120acf688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ad2d88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ad7788 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120adafc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120adf448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ae1b48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ae3f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120aea388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120af35c8 (
	input [3:0] a,
	output  r);
wire w_s1;
wire w_s2;
wire w_s8;
wire w_s10;
wire w_bits_1;
wire w_s4;
wire w_s6;
wire w_s0;
wire w_bits_2;
wire w_s3;
wire w_s9;
wire w_s5;
wire w_bits_0;
wire w_bits_3;
wire w_s7;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120af3f88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120af8c88 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120afd688 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120b00d88 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120b064c8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120b08fc8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120b0d708 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120b10e08 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120b15288 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120b18848 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120b1bc88 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120af3f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120af8c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120afd688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b00d88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b064c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b08fc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b0d708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b10e08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b15288 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b18848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b1bc88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120b25288 (
	input [3:0] a,
	output  r);
wire w_s1;
wire w_s4;
wire w_s10;
wire w_bits_0;
wire w_s9;
wire w_s11;
wire w_bits_3;
wire w_s5;
wire w_s6;
wire w_s8;
wire w_bits_1;
wire w_s2;
wire w_s3;
wire w_s7;
wire w_s0;
wire w_bits_2;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120b25c48 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120b2a688 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120b2ed88 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120b33788 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120b36e88 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120b3c708 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120b40108 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120b43808 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120b45f08 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120b4b248 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120b4e688 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120b51ac8 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b25c48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b2a688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b2ed88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b33788 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b36e88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b3c708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b40108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b43808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b45f08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b4b248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b4e688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b51ac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Digit7Segment_2b120b5e248 (
	input [3:0] v,
	output [6:0] led);
wire w_f;
wire w_nc;
wire w_ng;
wire w_c;
wire w_g;
wire w_nd;
wire w_d;
wire w_na;
wire w_ne;
wire w_e;
wire w_a;
wire w_nb;
wire w_nf;
wire w_b;

assign led ={w_g,w_f,w_e,w_d,w_c,w_b,w_a};
SumOfMinterms_2b120b5ec88 i_a(.a(v),.r(w_na));
SumOfMinterms_2b120b97a08 i_b(.a(v),.r(w_nb));
SumOfMinterms_2b120bc8748 i_c(.a(v),.r(w_nc));
SumOfMinterms_2b120c00448 i_d(.a(v),.r(w_nd));
SumOfMinterms_2b120c2e908 i_e(.a(v),.r(w_ne));
SumOfMinterms_2b120c5c788 i_f(.a(v),.r(w_nf));
SumOfMinterms_2b120c8f448 i_g(.a(v),.r(w_ng));
assign w_a = ~w_na;
assign w_b = ~w_nb;
assign w_c = ~w_nc;
assign w_d = ~w_nd;
assign w_e = ~w_ne;
assign w_f = ~w_nf;
assign w_g = ~w_ng;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120b5ec88 (
	input [3:0] a,
	output  r);
wire w_bits_2;
wire w_s3;
wire w_s7;
wire w_s11;
wire w_bits_0;
wire w_bits_3;
wire w_s8;
wire w_s9;
wire w_s1;
wire w_s2;
wire w_s6;
wire w_bits_1;
wire w_s4;
wire w_s5;
wire w_s10;
wire w_s0;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120b61c88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120b66988 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120b6c388 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120b6ea88 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120b731c8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120b76a08 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120b78e48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120b7e848 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120b80f48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120b86548 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120b89c48 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120b8e0c8 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b61c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b66988 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b6c388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b6ea88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b731c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b76a08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b78e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b7e848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b80f48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b86548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b89c48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b8e0c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120b97a08 (
	input [3:0] a,
	output  r);
wire w_bits_3;
wire w_s2;
wire w_s3;
wire w_s9;
wire w_bits_1;
wire w_s1;
wire w_s5;
wire w_s6;
wire w_s7;
wire w_bits_2;
wire w_s0;
wire w_s4;
wire w_s8;
wire w_bits_0;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120b9a408 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120b9f108 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120ba1ac8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120ba64c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120ba8bc8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120baf708 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120bb2b48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120bb6548 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120bb9c48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120bbf248 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b9a408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120b9f108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ba1ac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ba64c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ba8bc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120baf708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bb2b48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bb6548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bb9c48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bbf248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120bc8748 (
	input [3:0] a,
	output  r);
wire w_s6;
wire w_s9;
wire w_s2;
wire w_s7;
wire w_s8;
wire w_s0;
wire w_bits_2;
wire w_s3;
wire w_s4;
wire w_s11;
wire w_bits_0;
wire w_s5;
wire w_bits_3;
wire w_s10;
wire w_s1;
wire w_bits_1;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120bca148 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120bcde08 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120bd1808 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120bd4f08 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120bda908 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120bdf188 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120be1888 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120be5cc8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120be96c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120becc88 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120bf23c8 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120bf4808 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bca148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bcde08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bd1808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bd4f08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bda908 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bdf188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120be1888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120be5cc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120be96c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120becc88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bf23c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120bf4808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120c00448 (
	input [3:0] a,
	output  r);
wire w_bits_0;
wire w_s9;
wire w_bits_3;
wire w_s1;
wire w_s2;
wire w_s8;
wire w_bits_1;
wire w_s4;
wire w_s5;
wire w_s6;
wire w_s0;
wire w_s7;
wire w_bits_2;
wire w_s3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120c00e08 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120c04b08 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120c09508 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120c0cc08 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120c12348 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120c15b88 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120c19588 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120c1c9c8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120c22108 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120c25408 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c00e08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c04b08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c09508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c0cc08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c12348 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c15b88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c19588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c1c9c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c22108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c25408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120c2e908 (
	input [3:0] a,
	output  r);
wire w_s5;
wire w_bits_2;
wire w_s1;
wire w_s4;
wire w_s6;
wire w_s0;
wire w_bits_0;
wire w_s3;
wire w_s9;
wire w_bits_3;
wire w_s7;
wire w_s2;
wire w_bits_1;
wire w_s8;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120c31348 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120c35048 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120c37a08 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120c3e148 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120c41a08 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120c45288 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120c496c8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120c4bdc8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120c50248 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120c52548 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c31348 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c35048 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c37a08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c3e148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c41a08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c45288 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c496c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c4bdc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c50248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c52548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120c5c788 (
	input [3:0] a,
	output  r);
wire w_bits_1;
wire w_s2;
wire w_s4;
wire w_s6;
wire w_s9;
wire w_s10;
wire w_bits_2;
wire w_s0;
wire w_s3;
wire w_bits_0;
wire w_s5;
wire w_s7;
wire w_bits_3;
wire w_s1;
wire w_s8;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120c5e188 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120c60e48 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120c66848 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120c69f48 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120c6d688 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120c741c8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120c768c8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120c78fc8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120c7e448 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120c81a08 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120c83e48 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c5e188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c60e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c66848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c69f48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c6d688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c741c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c768c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c78fc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c7e448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c81a08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c83e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120c8f448 (
	input [3:0] a,
	output  r);
wire w_bits_0;
wire w_s10;
wire w_s11;
wire w_bits_3;
wire w_s4;
wire w_s5;
wire w_s6;
wire w_s8;
wire w_bits_1;
wire w_s2;
wire w_s3;
wire w_s9;
wire w_s0;
wire w_s7;
wire w_bits_2;
wire w_s1;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120c8fe08 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120c93848 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120c96f48 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120c9c948 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120ca0088 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120ca38c8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120ca92c8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120cac9c8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120cb1108 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120cb3408 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120cb6848 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120cb9c88 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c8fe08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c93848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c96f48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120c9c948 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ca0088 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ca38c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ca92c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cac9c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cb1108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cb3408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cb6848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cb9c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Digit7Segment_2b120cc7408 (
	input [3:0] v,
	output [6:0] led);
wire w_c;
wire w_g;
wire w_nd;
wire w_d;
wire w_na;
wire w_ne;
wire w_a;
wire w_e;
wire w_nb;
wire w_nf;
wire w_f;
wire w_nc;
wire w_ng;
wire w_b;

assign led ={w_g,w_f,w_e,w_d,w_c,w_b,w_a};
SumOfMinterms_2b120cc7e48 i_a(.a(v),.r(w_na));
SumOfMinterms_2b120cffbc8 i_b(.a(v),.r(w_nb));
SumOfMinterms_2b120d2f908 i_c(.a(v),.r(w_nc));
SumOfMinterms_2b120d68608 i_d(.a(v),.r(w_nd));
SumOfMinterms_2b120d95ac8 i_e(.a(v),.r(w_ne));
SumOfMinterms_2b120dc5a48 i_f(.a(v),.r(w_nf));
SumOfMinterms_2b120df7708 i_g(.a(v),.r(w_ng));
assign w_a = ~w_na;
assign w_b = ~w_nb;
assign w_c = ~w_nc;
assign w_d = ~w_nd;
assign w_e = ~w_ne;
assign w_f = ~w_nf;
assign w_g = ~w_ng;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120cc7e48 (
	input [3:0] a,
	output  r);
wire w_s11;
wire w_bits_0;
wire w_bits_3;
wire w_s6;
wire w_s3;
wire w_s9;
wire w_s1;
wire w_s2;
wire w_s7;
wire w_s8;
wire w_bits_1;
wire w_s4;
wire w_s10;
wire w_s5;
wire w_s0;
wire w_bits_2;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120cc9e48 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120cceb48 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120cd3548 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120cd7c48 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120cdc388 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120cdfbc8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120ce4048 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120ce6a08 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120ceb148 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120ced708 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120cf2e08 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120cf7288 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cc9e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cceb48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cd3548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cd7c48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cdc388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cdfbc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ce4048 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ce6a08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ceb148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ced708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cf2e08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120cf7288 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120cffbc8 (
	input [3:0] a,
	output  r);
wire w_s2;
wire w_s3;
wire w_bits_1;
wire w_s1;
wire w_s5;
wire w_s8;
wire w_s6;
wire w_s7;
wire w_bits_2;
wire w_s0;
wire w_s4;
wire w_bits_0;
wire w_s9;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120d015c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120d072c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120d09c88 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120d0f688 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120d12d88 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120d168c8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120d1ad08 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120d1e708 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120d21e08 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120d28408 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d015c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d072c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d09c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d0f688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d12d88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d168c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d1ad08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d1e708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d21e08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d28408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120d2f908 (
	input [3:0] a,
	output  r);
wire w_s7;
wire w_s8;
wire w_s9;
wire w_bits_2;
wire w_s0;
wire w_s4;
wire w_s3;
wire w_bits_0;
wire w_s5;
wire w_bits_3;
wire w_s10;
wire w_s1;
wire w_s2;
wire w_s11;
wire w_bits_1;
wire w_s6;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120d32308 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120d35fc8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120d3b9c8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120d40108 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120d43ac8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120d48348 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120d4aa48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120d4de88 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120d52888 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120d56e48 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120d5b588 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120d5e9c8 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d32308 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d35fc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d3b9c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d40108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d43ac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d48348 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d4aa48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d4de88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d52888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d56e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d5b588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d5e9c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120d68608 (
	input [3:0] a,
	output  r);
wire w_bits_3;
wire w_s1;
wire w_s2;
wire w_s8;
wire w_bits_1;
wire w_s4;
wire w_s5;
wire w_s6;
wire w_s0;
wire w_s7;
wire w_bits_2;
wire w_s3;
wire w_s9;
wire w_bits_0;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120d68fc8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120d6ecc8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120d736c8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120d76dc8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120d7a508 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120d7ed48 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120d83748 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120d86b88 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120d8c2c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120d8e5c8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d68fc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d6ecc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d736c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d76dc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d7a508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d7ed48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d83748 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d86b88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d8c2c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d8e5c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120d95ac8 (
	input [3:0] a,
	output  r);
wire w_bits_2;
wire w_s0;
wire w_s4;
wire w_s7;
wire w_bits_0;
wire w_s3;
wire w_s8;
wire w_bits_3;
wire w_s5;
wire w_s6;
wire w_bits_1;
wire w_s2;
wire w_s1;
wire w_s9;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120d98508 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120da0208 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120da2bc8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120da6308 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120daacc8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120dae548 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120db1988 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120db70c8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120dba508 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120dbc808 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120d98508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120da0208 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120da2bc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120da6308 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120daacc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dae548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120db1988 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120db70c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dba508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dbc808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120dc5a48 (
	input [3:0] a,
	output  r);
wire w_bits_0;
wire w_s5;
wire w_bits_3;
wire w_s7;
wire w_s9;
wire w_bits_2;
wire w_s2;
wire w_s8;
wire w_bits_1;
wire w_s1;
wire w_s4;
wire w_s10;
wire w_s6;
wire w_s0;
wire w_s3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120dc7448 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120dcc148 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120dcfb08 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120dd5248 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120dd7948 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120ddc488 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120ddfb88 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120de42c8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120de6708 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120deacc8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120df0148 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dc7448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dcc148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dcfb08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dd5248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dd7948 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ddc488 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ddfb88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120de42c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120de6708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120deacc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120df0148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120df7708 (
	input [3:0] a,
	output  r);
wire w_s7;
wire w_bits_2;
wire w_s0;
wire w_s3;
wire w_s9;
wire w_s1;
wire w_s10;
wire w_bits_0;
wire w_s4;
wire w_s11;
wire w_bits_3;
wire w_s5;
wire w_s6;
wire w_s8;
wire w_bits_1;
wire w_s2;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120df9108 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120dfcb08 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120e02248 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120e05c08 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120e0a348 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120e0db88 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120e12588 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120e14c88 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120e1a3c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120e1d6c8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120e21b08 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120e23f48 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120df9108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120dfcb08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e02248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e05c08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e0a348 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e0db88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e12588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e14c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e1a3c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e1d6c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e21b08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e23f48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Digit7Segment_2b120e316c8 (
	input [3:0] v,
	output [6:0] led);
wire w_b;
wire w_f;
wire w_nc;
wire w_ng;
wire w_c;
wire w_g;
wire w_nd;
wire w_d;
wire w_na;
wire w_ne;
wire w_a;
wire w_nf;
wire w_nb;
wire w_e;

assign led ={w_g,w_f,w_e,w_d,w_c,w_b,w_a};
SumOfMinterms_2b120e33148 i_a(.a(v),.r(w_na));
SumOfMinterms_2b120e69e88 i_b(.a(v),.r(w_nb));
SumOfMinterms_2b120e9abc8 i_c(.a(v),.r(w_nc));
SumOfMinterms_2b120ed28c8 i_d(.a(v),.r(w_nd));
SumOfMinterms_2b120f00d88 i_e(.a(v),.r(w_ne));
SumOfMinterms_2b120f2dd08 i_f(.a(v),.r(w_nf));
SumOfMinterms_2b120f619c8 i_g(.a(v),.r(w_ng));
assign w_a = ~w_na;
assign w_b = ~w_nb;
assign w_c = ~w_nc;
assign w_d = ~w_nd;
assign w_e = ~w_ne;
assign w_f = ~w_nf;
assign w_g = ~w_ng;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120e33148 (
	input [3:0] a,
	output  r);
wire w_s5;
wire w_s7;
wire w_s0;
wire w_bits_2;
wire w_s3;
wire w_s6;
wire w_s2;
wire w_s10;
wire w_s11;
wire w_bits_0;
wire w_s8;
wire w_bits_3;
wire w_s9;
wire w_s1;
wire w_bits_1;
wire w_s4;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120e36148 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120e39e08 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120e3e808 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120e41f08 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120e46648 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120e49e88 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120e4e308 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120e50cc8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120e57408 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120e599c8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120e5d108 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120e61548 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e36148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e39e08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e3e808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e41f08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e46648 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e49e88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e4e308 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e50cc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e57408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e599c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e5d108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e61548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120e69e88 (
	input [3:0] a,
	output  r);
wire w_bits_2;
wire w_s9;
wire w_bits_0;
wire w_s8;
wire w_bits_3;
wire w_s2;
wire w_s3;
wire w_s1;
wire w_s5;
wire w_bits_1;
wire w_s4;
wire w_s6;
wire w_s7;
wire w_s0;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120e6b888 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120e71588 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120e74f48 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120e78948 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120e7f088 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120e81b88 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120e83fc8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120e899c8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120e8e108 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120e916c8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e6b888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e71588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e74f48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e78948 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e7f088 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e81b88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e83fc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e899c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e8e108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e916c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120e9abc8 (
	input [3:0] a,
	output  r);
wire w_s2;
wire w_s11;
wire w_bits_1;
wire w_s1;
wire w_s6;
wire w_s5;
wire w_s8;
wire w_s9;
wire w_s0;
wire w_bits_2;
wire w_s4;
wire w_s7;
wire w_s3;
wire w_s10;
wire w_bits_0;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120e9d5c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120ea12c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120ea4c88 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120ea93c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120eacd88 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120eb2608 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120eb3d08 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120eb9188 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120ebcb48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120ec0148 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120ec4848 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120ec7c88 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120e9d5c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ea12c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ea4c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ea93c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120eacd88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120eb2608 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120eb3d08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120eb9188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ebcb48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ec0148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ec4848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ec7c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120ed28c8 (
	input [3:0] a,
	output  r);
wire w_s0;
wire w_bits_2;
wire w_s9;
wire w_s3;
wire w_bits_0;
wire w_bits_3;
wire w_s1;
wire w_s2;
wire w_s8;
wire w_bits_1;
wire w_s4;
wire w_s5;
wire w_s7;
wire w_s6;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120ed42c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120ed7f88 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120edb988 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120ee20c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120ee57c8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120ee9048 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120eeca08 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120eefe48 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120ef3588 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120ef6888 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ed42c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ed7f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120edb988 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ee20c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ee57c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ee9048 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120eeca08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120eefe48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ef3588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ef6888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120f00d88 (
	input [3:0] a,
	output  r);
wire w_s2;
wire w_bits_1;
wire w_s1;
wire w_s9;
wire w_s6;
wire w_bits_2;
wire w_s0;
wire w_s4;
wire w_s7;
wire w_bits_0;
wire w_s3;
wire w_s8;
wire w_s5;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120f027c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120f064c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120f0ae88 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120f0e5c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120f11f88 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120f18808 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120f1bc48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120f1f388 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120f217c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120f24ac8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f027c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f064c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f0ae88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f0e5c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f11f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f18808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f1bc48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f1f388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f217c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f24ac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120f2dd08 (
	input [3:0] a,
	output  r);
wire w_s0;
wire w_bits_2;
wire w_s3;
wire w_s1;
wire w_bits_0;
wire w_s5;
wire w_s7;
wire w_s9;
wire w_bits_3;
wire w_s2;
wire w_s8;
wire w_bits_1;
wire w_s10;
wire w_s6;
wire w_s4;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120f30708 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120f36408 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120f38dc8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120f3d508 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120f40c08 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120f46748 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120f49e48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120f4e588 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120f509c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120f53f88 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120f58408 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f30708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f36408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f38dc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f3d508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f40c08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f46748 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f49e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f4e588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f509c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f53f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f58408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120f619c8 (
	input [3:0] a,
	output  r);
wire w_s8;
wire w_s5;
wire w_bits_1;
wire w_s3;
wire w_s2;
wire w_s7;
wire w_s0;
wire w_bits_2;
wire w_s9;
wire w_s1;
wire w_s10;
wire w_s6;
wire w_bits_0;
wire w_s4;
wire w_bits_3;
wire w_s11;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120f633c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120f66dc8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120f6b508 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120f6fec8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120f74608 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120f76e48 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120f7d848 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120f7ff48 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120f83688 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120f86988 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120f89dc8 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120f8e248 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f633c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f66dc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f6b508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f6fec8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f74608 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f76e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f7d848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f7ff48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f83688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f86988 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f89dc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f8e248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Digit7Segment_2b120f969c8 (
	input [3:0] v,
	output [6:0] led);
wire w_nd;
wire w_d;
wire w_g;
wire w_na;
wire w_ne;
wire w_e;
wire w_a;
wire w_nb;
wire w_nf;
wire w_b;
wire w_f;
wire w_nc;
wire w_ng;
wire w_c;

assign led ={w_g,w_f,w_e,w_d,w_c,w_b,w_a};
SumOfMinterms_2b120f9c448 i_a(.a(v),.r(w_na));
SumOfMinterms_2b120fd31c8 i_b(.a(v),.r(w_nb));
SumOfMinterms_2b121001ec8 i_c(.a(v),.r(w_nc));
SumOfMinterms_2b12103cbc8 i_d(.a(v),.r(w_nd));
SumOfMinterms_2b12106c0c8 i_e(.a(v),.r(w_ne));
SumOfMinterms_2b121099048 i_f(.a(v),.r(w_nf));
SumOfMinterms_2b1210cacc8 i_g(.a(v),.r(w_ng));
assign w_a = ~w_na;
assign w_b = ~w_nb;
assign w_c = ~w_nc;
assign w_d = ~w_nd;
assign w_e = ~w_ne;
assign w_f = ~w_nf;
assign w_g = ~w_ng;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120f9c448 (
	input [3:0] a,
	output  r);
wire w_bits_0;
wire w_bits_3;
wire w_s9;
wire w_s2;
wire w_s8;
wire w_s11;
wire w_bits_1;
wire w_s1;
wire w_s4;
wire w_s10;
wire w_s5;
wire w_s7;
wire w_s0;
wire w_s6;
wire w_s3;
wire w_bits_2;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120f9e448 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120fa3148 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120fa6b08 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120fac248 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120fae948 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120fb51c8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120fb8608 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120fbafc8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120fbe708 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120fc2cc8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b120fc7408 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b120fc9848 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120f9e448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fa3148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fa6b08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fac248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fae948 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fb51c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fb8608 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fbafc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fbe708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fc2cc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fc7408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fc9848 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b120fd31c8 (
	input [3:0] a,
	output  r);
wire w_s1;
wire w_s2;
wire w_s5;
wire w_s8;
wire w_bits_1;
wire w_s7;
wire w_s6;
wire w_s0;
wire w_bits_2;
wire w_s4;
wire w_s9;
wire w_bits_0;
wire w_s3;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b120fd3b88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b120fd8888 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b120fe0288 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b120fe1c48 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b120fe6388 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b120feae88 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b120fef308 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b120ff2cc8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b120ff8408 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b120ffb9c8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fd3b88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fd8888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fe0288 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fe1c48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fe6388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120feae88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120fef308 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ff2cc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ff8408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b120ffb9c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b121001ec8 (
	input [3:0] a,
	output  r);
wire w_s0;
wire w_s7;
wire w_bits_2;
wire w_s3;
wire w_s4;
wire w_s9;
wire w_s5;
wire w_s6;
wire w_bits_0;
wire w_s10;
wire w_bits_3;
wire w_s2;
wire w_s11;
wire w_s1;
wire w_bits_1;
wire w_s8;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b1210058c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b12100a5c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b12100df88 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b1210136c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b1210180c8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b12101a908 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b121020048 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b121021488 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b121025e48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b12102b448 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b12102eb48 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b12102ff88 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210058c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12100a5c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12100df88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210136c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210180c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12101a908 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121020048 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121021488 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121025e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12102b448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12102eb48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12102ff88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b12103cbc8 (
	input [3:0] a,
	output  r);
wire w_s2;
wire w_s8;
wire w_bits_1;
wire w_s1;
wire w_s4;
wire w_s6;
wire w_s5;
wire w_bits_2;
wire w_s0;
wire w_s7;
wire w_s9;
wire w_s3;
wire w_bits_0;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b12103d5c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b1210442c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b121047c88 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b12104b3c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b12104eac8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b121054348 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b121056d08 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b12105c188 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b12105f888 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b121062b88 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12103d5c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210442c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121047c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12104b3c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12104eac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121054348 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121056d08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12105c188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12105f888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121062b88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b12106c0c8 (
	input [3:0] a,
	output  r);
wire w_bits_2;
wire w_s0;
wire w_s7;
wire w_s3;
wire w_s4;
wire w_s8;
wire w_bits_0;
wire w_s5;
wire w_bits_3;
wire w_s6;
wire w_bits_1;
wire w_s1;
wire w_s2;
wire w_s9;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b12106cac8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b1210717c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b1210771c8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b12107a8c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b12107e2c8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b121081b08 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b121083f48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b121089688 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b12108cac8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b12108fdc8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12106cac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210717c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210771c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12107a8c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12107e2c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121081b08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121083f48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121089688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12108cac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12108fdc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b121099048 (
	input [3:0] a,
	output  r);
wire w_bits_0;
wire w_s7;
wire w_bits_3;
wire w_s8;
wire w_s9;
wire w_s1;
wire w_s2;
wire w_s4;
wire w_s10;
wire w_bits_1;
wire w_s6;
wire w_s0;
wire w_s3;
wire w_bits_2;
wire w_s5;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b121099a08 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b12109e708 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b1210a4108 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b1210a7808 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b1210aaf08 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b1210afa48 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b1210b4188 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b1210b7888 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b1210b9cc8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b1210be2c8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b1210c2708 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121099a08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12109e708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210a4108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210a7808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210aaf08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210afa48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210b4188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210b7888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210b9cc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210be2c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210c2708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b1210cacc8 (
	input [3:0] a,
	output  r);
wire w_s0;
wire w_s3;
wire w_s7;
wire w_s9;
wire w_bits_2;
wire w_bits_0;
wire w_s1;
wire w_s4;
wire w_s10;
wire w_s6;
wire w_s11;
wire w_bits_3;
wire w_s5;
wire w_s8;
wire w_bits_1;
wire w_s2;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b1210cb6c8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b1210d1108 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b1210d5808 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b1210d9208 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b1210dd908 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b1210e2188 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b1210e4b48 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b1210ea288 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b1210ec988 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b1210f0c88 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b1210f4108 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b1210f8548 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210cb6c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210d1108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210d5808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210d9208 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210dd908 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210e2188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210e4b48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210ea288 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210ec988 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210f0c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210f4108 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1210f8548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Digit7Segment_2b121101c88 (
	input [3:0] v,
	output [6:0] led);
wire w_b;
wire w_f;
wire w_nc;
wire w_ng;
wire w_c;
wire w_g;
wire w_nd;
wire w_d;
wire w_na;
wire w_ne;
wire w_a;
wire w_e;
wire w_nb;
wire w_nf;

assign led ={w_g,w_f,w_e,w_d,w_c,w_b,w_a};
SumOfMinterms_2b121106708 i_a(.a(v),.r(w_na));
SumOfMinterms_2b12113e488 i_b(.a(v),.r(w_nb));
SumOfMinterms_2b12116f1c8 i_c(.a(v),.r(w_nc));
SumOfMinterms_2b1211a4e88 i_d(.a(v),.r(w_nd));
SumOfMinterms_2b1211d4388 i_e(.a(v),.r(w_ne));
SumOfMinterms_2b121203308 i_f(.a(v),.r(w_nf));
SumOfMinterms_2b121234f88 i_g(.a(v),.r(w_ng));
assign w_a = ~w_na;
assign w_b = ~w_nb;
assign w_c = ~w_nc;
assign w_d = ~w_nd;
assign w_e = ~w_ne;
assign w_f = ~w_nf;
assign w_g = ~w_ng;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b121106708 (
	input [3:0] a,
	output  r);
wire w_s5;
wire w_s1;
wire w_s0;
wire w_s6;
wire w_s7;
wire w_s10;
wire w_bits_2;
wire w_s3;
wire w_s11;
wire w_bits_0;
wire w_s9;
wire w_bits_3;
wire w_s2;
wire w_s8;
wire w_bits_1;
wire w_s4;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b121108708 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b12110d408 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b12110fdc8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b121115508 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b121118c08 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b12111c488 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b12111f8c8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b1211262c8 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b1211279c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b12112af88 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b12112f6c8 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b121133b08 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121108708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12110d408 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12110fdc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121115508 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121118c08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12111c488 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12111f8c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211262c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211279c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12112af88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12112f6c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121133b08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b12113e488 (
	input [3:0] a,
	output  r);
wire w_s9;
wire w_bits_0;
wire w_s8;
wire w_bits_3;
wire w_s3;
wire w_s1;
wire w_s2;
wire w_bits_1;
wire w_s5;
wire w_s7;
wire w_s6;
wire w_s4;
wire w_s0;
wire w_bits_2;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b12113ee48 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b121143b48 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b121148548 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b12114bf08 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b121151648 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b121156188 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b1211595c8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b12115af88 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b1211616c8 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b121163c88 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12113ee48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121143b48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;
wire w_n2;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121148548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12114bf08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121151648 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121156188 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211595c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12115af88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211616c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121163c88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b12116f1c8 (
	input [3:0] a,
	output  r);
wire w_s1;
wire w_s2;
wire w_s11;
wire w_bits_1;
wire w_s6;
wire w_s9;
wire w_s0;
wire w_s7;
wire w_s8;
wire w_bits_2;
wire w_s3;
wire w_s4;
wire w_s5;
wire w_s10;
wire w_bits_0;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b12116fb88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b121174888 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b121179288 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b12117c988 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b121182388 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b121183bc8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b12118a308 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b12118c748 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b121190148 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b121193708 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b121197e08 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b12119c288 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12116fb88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121174888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121179288 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12117c988 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121182388 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121183bc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12118a308 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;

assign w_n3 = ~b3;
assign r = b0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12118c748 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121190148 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121193708 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121197e08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12119c288 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b1211a4e88 (
	input [3:0] a,
	output  r);
wire w_bits_2;
wire w_s3;
wire w_bits_0;
wire w_bits_3;
wire w_s2;
wire w_s7;
wire w_s8;
wire w_s1;
wire w_s4;
wire w_bits_1;
wire w_s6;
wire w_s5;
wire w_s9;
wire w_s0;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b1211a7888 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b1211ab588 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b1211aef48 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b1211b5688 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b1211b7d88 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b1211bc608 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b1211bffc8 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b1211c4448 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b1211c6b48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b1211c9e48 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211a7888 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211ab588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211aef48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n3;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211b5688 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211b7d88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211bc608 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211bffc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211c4448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211c6b48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211c9e48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b1211d4388 (
	input [3:0] a,
	output  r);
wire w_bits_1;
wire w_s1;
wire w_s2;
wire w_s9;
wire w_s0;
wire w_bits_2;
wire w_s7;
wire w_s3;
wire w_s4;
wire w_s8;
wire w_bits_0;
wire w_s5;
wire w_bits_3;
wire w_s6;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b1211d4d88 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b1211d9a88 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b1211de488 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b1211e1b88 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b1211e7588 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b1211ebdc8 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b1211f0248 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b1211f2948 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b1211f5d88 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b1211fa0c8 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211d4d88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n1;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211d9a88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211de488 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211e1b88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211e7588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211ebdc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211f0248 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211f2948 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211f5d88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1211fa0c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b121203308 (
	input [3:0] a,
	output  r);
wire w_s0;
wire w_s4;
wire w_bits_2;
wire w_s3;
wire w_s5;
wire w_bits_0;
wire w_s7;
wire w_bits_3;
wire w_s8;
wire w_s9;
wire w_s1;
wire w_s2;
wire w_s10;
wire w_bits_1;
wire w_s6;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b121203cc8 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b1212089c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b12120d3c8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b121210ac8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b121215208 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b121218d08 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b12121d448 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b12121fb48 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b121223f88 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b121228588 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b12122a9c8 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121203cc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;
wire w_n3;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1212089c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12120d3c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121210ac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n3;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121215208 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;
wire w_n2;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121218d08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12121d448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12121fb48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121223f88 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign r = w_n0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121228588 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12122a9c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module SumOfMinterms_2b121234f88 (
	input [3:0] a,
	output  r);
wire w_bits_1;
wire w_s2;
wire w_s3;
wire w_s11;
wire w_s0;
wire w_s7;
wire w_s5;
wire w_s6;
wire w_bits_2;
wire w_s9;
wire w_s1;
wire w_s4;
wire w_s10;
wire w_bits_0;
wire w_s8;
wire w_bits_3;

assign w_bits_0 = a[0];
assign w_bits_1 = a[1];
assign w_bits_2 = a[2];
assign w_bits_3 = a[3];
Minterm_2b121236988 i_minterm0(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s0));
Minterm_2b12123a3c8 i_minterm1(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s1));
Minterm_2b12123eac8 i_minterm2(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s2));
Minterm_2b1212434c8 i_minterm3(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s3));
Minterm_2b121245bc8 i_minterm4(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s4));
Minterm_2b12124c448 i_minterm5(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s5));
Minterm_2b12124ee08 i_minterm6(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s6));
Minterm_2b121253548 i_minterm7(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s7));
Minterm_2b121255c48 i_minterm8(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s8));
Minterm_2b121258f48 i_minterm9(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s9));
Minterm_2b12125e3c8 i_minterm10(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s10));
Minterm_2b121261808 i_minterm11(.b0(w_bits_0),.b1(w_bits_1),.b2(w_bits_2),.b3(w_bits_3),.r(w_s11));
assign r = w_s0 | w_s1 | w_s2 | w_s3 | w_s4 | w_s5 | w_s6 | w_s7 | w_s8 | w_s9 | w_s10 | w_s11 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121236988 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;
wire w_n2;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12123a3c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n2;

assign w_n2 = ~b2;
assign w_n3 = ~b3;
assign r = b0 & b1 & w_n2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12123eac8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;
wire w_n1;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = w_n0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b1212434c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n1;

assign w_n1 = ~b1;
assign w_n3 = ~b3;
assign r = b0 & w_n1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121245bc8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n3;
wire w_n0;

assign w_n0 = ~b0;
assign w_n3 = ~b3;
assign r = w_n0 & b1 & b2 & w_n3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12124c448 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = w_n0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12124ee08 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n1;

assign w_n1 = ~b1;
assign w_n2 = ~b2;
assign r = b0 & w_n1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121253548 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;
wire w_n0;

assign w_n0 = ~b0;
assign w_n2 = ~b2;
assign r = w_n0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121255c48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n2;

assign w_n2 = ~b2;
assign r = b0 & b1 & w_n2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121258f48 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n1;

assign w_n1 = ~b1;
assign r = b0 & w_n1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b12125e3c8 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);
wire w_n0;

assign w_n0 = ~b0;
assign r = w_n0 & b1 & b2 & b3 ;
endmodule

// This file was automatically created by py4hw RTL generator
module Minterm_2b121261808 (
	input  b0,
	input  b1,
	input  b2,
	input  b3,
	output  r);

assign r = b0 & b1 & b2 & b3 ;
endmodule